Calibre DesignEnhancer design-stage layout optimization for EMIR

The innovative Calibre DesignEnhancer tool lets IC design companies implement shift left design flows to resolve EM, ESD, and IR drop challenges earlier with correct by construction design-stage layout optimization. The Calibre DesignEnhancer use models employ analysis-based capabilities in the Calibre nmPlatform to automatically implement DRC-clean DFM modifications during design implementation. Customers demonstrate their use of Calibre DesignEnhancer layout optimization, and the improvements they achieved, including layout modification results and EM/IR improvements resulting from these modifications.

Resolve EM, ESD, and IR drop challenges earlier with Calibre confidence

EM, ESD, and IR drop issues can delay design implementation and derail tapeout schedules. The Calibre DesignEnhancer tool enables IC design companies to apply automated, correct-by-construction layout optimizations to improve design reliability and power management during design implementation. Intel Foundry Services and Juniper Networks share their use of the Calibre DesignEnhancer tool on real-world designs and the improvements they achieved.