Conquer 3D IC thermal impacts with Calibre 3DThermal
Thermal design inside the Calibre IC design ecosystem for IC and packaging designers
The Calibre 3DThermal tool lets designers perform accurate chip and package-level static or dynamic thermal analysis of the full 3D IC assembly. It combines a customized solver engine from the industry-leading 3D package-level thermal analysis tool, Simcenter Flotherm, and the proven Calibre physical verification platform to perform highly accurate and computationally efficient thermal analysis.
Calibre 3DThermal is part of Calibre's multiphysics verification solution designed to mitigate the complex interplay between thermal impacts, mechanical stress and electrical behavior in 3D IC designs, helping design teams optimize their productivity while improving design quality. With Calibre 3DThermal, designers of 3D ICs now have an integrated chip-package thermal co-design flow that spans early-stage package exploration through design signoff.
Who should read this:
- IC designers focused on chiplet design with little experience with traditional thermal analysis
- Package designers creating any type of multi-die advanced package
- Thermal analysts focusing on electronics
What you'll learn:
- Why 3DI Cs need die-level and die-package thermal analysis
- The importance of advanced automation to IC designers who are not thermal/CFD experts
- How to capture, visualize and debug thermal issues
- How the Calibre 3DThermal tool provides accurate thermal analysis from early-stage package exploration to design signoff and is part of a die-package-system thermal analysis solution
- Examples of industry usage of the Calibre 3DThermal tool.
"We want to evaluate the thermal performance of a given system-in-package (SiP) or chiplet design much faster and more efficiently than we have ever done before. Existing workflows take a lot of time just to set up the analyses and need to driven by thermal experts, of which there are few. With Siemens new thermal workflow based on Calibre 3DThermal, we are able to quickly evaluate micro-architectures for thermal performance in a SiP/chiplet design." --Intel design team.