Accelerate early design exploration and verification for faster time to market

Early chip-level physical verification faces many challenges. The Calibre nmDRC Recon tool enables design teams to perform analysis and physical verification of full-chip design layouts during very early stages of the design cycle, while the different components are still immature. With Calibre nmDRC Recon technology, designers can quickly and easily find and resolve integration issues using the foundry/IDM Calibre sign-off design kit, while reducing total DRC runtime, accelerating design closure, and ensuring high-quality designs.

Quickly find and resolve SoC integration issues while reducing total DRC runtimes

SoC designers typically start chip integration in parallel with block development to capture and correct any routing violations early in the design cycle. However, during very early phases of floorplanning, many systematic issues are widely distributed across the design, making it difficult to differentiate between block-level violations and top-level routing violations. The Calibre nmDRC Recon tool automatically deselects checks that are not relevant for the current development phase, with the goal of providing good coverage, fast runtime, and less memory consumption.

On average, the Calibre nmDRC Recon tool reduces overall DRC runtime by up to 14x, while still checking ~50 percent of the total DRC set. The subset of rules automatically selected by the Calibre engine are effective in identifying floorplan and sub-chip integration issues, providing fast feedback to the design team for proper corrective action and resulting in a significantly reduced total turnaround time.