QuestaSim

In addition to the sheer size of designs and the inclusion of multiple embedded processors and advanced interconnect systems, the increase in software content and the configurability required by multi-platform design require a functional verification solution that unifies a broad arsenal of verification features. This places tremendous importance on having a verification plan informed by the collection of coverage metrics that track progress against the plan throughout the verification process. This intelligent verification plan enables engineers to allocate and manage resources efficiently and identify trends as the project progresses.

The QuestaSim verification solution delivers on these requirements for complex SoC designs. QuestaSim achieves industry-leading performance and capacity through aggressive, global compile and simulation optimization algorithms for SystemVerilog, VHDL, and SystemC. Meanwhile, its Questa Visualizer debug environment provides high-performance, high-capacity debugging for dramatic regression throughput improvements when running large test suites.

QuestaSim Benefits

• Industry-leading high performance multi-language simulator
• High-performance, high-capacity
  unified debug
• Reference simulator for LRM compatibility
• UVM, SystemVerilog, VHDL, SystemC,
  and mixed language support
• Native compiled, single kernel simulator technology
• Next generation Visualizer debug environment
• Code coverage and functional coverage
• SVA and PSL assertions
• Intelligent coverage closure
• Integrated verification management
  and analysis
• Simulate in advanced optimization mode
• Best-in-class power-aware
  verification technology
• Profiling for hotspot analysis
• C code debug
• X-propagation dynamic simulation
• Real number modeling
• Common coverage database and flows