Without objection

The SystemVerilog UVM implements a class named uvm_objection. An objection is used to guard code that “isn't done yet.” For example, an objection can prevent a process from finishing until some other process agrees. uvm_objections are sometimes overused and are always misunderstood. This paper explains the implementations, shares uses, and provides some alternative solutions that are easier to understand, simpler to use, and work transparently.

Making objections straightforward

Synchronization with objections is conceptually simple—raise an objection to “passing the barrier” and drop an objection to “passing the barrier.” But the UVM phasing and objection code quickly become intertwined. There’s complexity there that can be problematic to debug and understand. Simple synchronization can be implemented with something much simpler.

The SystemVerilog uvm_objection is a powerful tool. It is used widely to coordinate processes—in most UVM testbenches. But use it wisely, as with the right set of calls it can hang itself without any testbench or DUT.

The solutions presented in this paper are easier to understand, simpler to use, and work transparently. Source code shared in this paper is available by request from the author.