为独立电子制造商提供更快、更准确的报价 (1)

Currently hierarchical data models (HDM) must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the source of the generated model.

For large designs with numerous asynchronous clocks and resets, there is a growing need to do hierarchical clock domain and reset domain crossing analysis. This allows parallelization of sub-block and noiseless analysis, reduces SoC runtimes, and speeds closure of CDC and RDC issues at the SoC level.

However, it poses challenges for design houses using third-party IP who need to ensure the compatibility of their HDMs across multiple EDA tools. To protect their IP, vendors rarely provide the RTL source code, providing HDMs for their IPs instead. Currently HDMs need to be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level.

To support the use of multi-vendor tool flows, the Accellera CDC Working Group was formed to create a standard format for HDMs so these models can be consumed by any EDA tool irrespective of their source. This helps the design community by making them independent of any particular EDA tool when it comes to doing CDC and RDC analysis.