Pushing PPA with HPCWorks Flowtracer – advanced usage models for physical chip design
Explore six real-world failure modes that can be prevented with an integrated multiphysics simulation strategy
Semiconductor companies face daunting challenges related to chip design and verification. These challenges include increased competition, larger and more complex designs, time-to-market pressures and limited budgets for infrastructure and tools. Improvements in processor speed have slowed, causing organizations to look for new ways to improve efficiency.
Why read the white paper:
Understand how HPCWorks Flowtracer dynamically redefines physical design flows, optimizes PPA in chip design with a branch-and-prune strategy, and empowers designers with control and reproducibility.
- Understand advanced usage models, such as branching and pruning
- Leverage HPCWorks Flowtracer for reproducibility and designer control
- Gain insights into automating optimization with meta-flows
What you'll learn:
You’ll discover how HPCWorks Flowtracer optimizes physical chip design flows for PPA.
- Enables efficient experimentation with design parameters
- Improves design flow efficiency and automation
- Identifies best-known methods for chip design