PCIe Simulation Speed-Up Using Questa VIP with PLDA PCIe Controller for DMA Applications

In this case study, PLDA explains how verification engineers can use Questa Verification IP (QVIP) to improve productivity during the functional verification of PCIe designs with DMA engines. The flexibility of Questa VIP was key to creating custom testbenches from scratch that can dynamically adapt to different IP topologies and configurations, mixing PCIe interfaces with multiple AXI interfaces. PLDA and Siemens EDA have collaborated throughout the different PCIe generations, enabling advanced leadership on the latest technologies together.