Functional verification of analog devices modeled using SV-RNM

New functional verification models are introduced, from random stimulus, functional coverage, assertions, and UVM on the Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) devices, to ensure that the modeled ADC/DAC devices are designed correctly according to the system specifications and requirements.

Ensuring correct functionality of ADC/DAC devices

In the digital environment, there are a lot of verification techniques that can be used to find bugs within a system. For this reason, digital verification is always preferred due to its reliability and history of usage. Only one environment and one event-driven simulator can provide these verification techniques in an automated way.

This paper illustrates new functional verification models that ensure the correct functionality of ADC/DAC devices, using:

Constrained random verification
From this step, digital verification engineers are able to know the extent of the variation that each component can hold without causing the system to behave incorrectly.

Functional coverage
This technique ensures that the electrical voltage is covered under a certain amplitude range.

Assertions
Assertions are used to check the functionality of the whole system to see if there is a simple relation between the output and input of a system.

UVM-based verification
The UVM testbench environment provides classes to support the randomization of ports through “uvm_sequence” class and supports functional coverage through the “uvm_subscriber” class and assertions through the “uvm_scoreboard” class.