用于船舶设计的全尺寸 CFD 仿真：深度述评
计算流体力学 (CFD) 在船舶设计中应用广泛。CFD 通常在模型级别运行，以便与试验槽验证数据进行比较。但是，由于无法观察到雷诺数的缩放，因此很难将模型尺寸结果转换为全尺寸结果。这意味着模型尺寸的理想设计通常不符合全尺寸的要求。在模型尺寸上，研究不同比例的船舶组件（例如，船体-螺旋桨相互作用或节能装置）之间的相互作用也并非易事。在本白皮书中，米洛万·佩里奇 (Milovan Peric) 教授探讨了针对运行全尺寸 CFD 仿真的一些常见保留意见，并鼓励在实际操作条件下对船舶设计进行全尺寸分析。
尺度分析示例
作者研究了一些尺度分析示例，例如雷诺数缩放的影响，以及计算网格要求，同时列举了在复杂情况下进行全尺寸 CFD 仿真的示例。在很多情况下，全尺寸仿真都比其他备选方案更加准确而可靠，因而也更有助于理解设计性能。
船舶结构分析与设计
全尺寸船舶结构分析与设计以及完整系统需要数字孪生技术。
借助功能强大的软件，可以执行仿真来镜像真实操作条件以确保找到合适的设计。此行业许多资深用户已成功应用全尺寸 CFD 仿真，阅读此述评，了解全尺寸 CFD 的诸多优势。
尺度预测软件
此船舶行业资料提供全尺寸预测软件用例等。在很多情况下，全尺寸预测比缩尺模型实验更加可靠。
相关资源
LG Electronics: Video Encoder IP Design Optimization and Verification Using Catapult
In this session, LGE describes a new design approach which concluded that adopting Catapult in IP development increases efficiency in time and cost, and they plan to increase usage in future IP projects.
NVIDIA: High-Level Synthesis in Agile System-on-Chip Flows: Overview and Techniques
This talk provides a brief overview of NVIDIA Research’s use of Catapult HLS and highlights some useful features and flows of the Connections library, such as the ability to back-annotate SystemC simulations.
Catapult AI NN – From AI/ML Framework to Optimized RTL
Video describing how Catapult AI NN now delivers a methodology and flow from “AI/ML Framework to RTL” enabling rapid exploration of network, quantization, design reuse factors, and more!
High-Level Synthesis Verification Technologies and Techniques
This session will describe applying known and trusted static, formal and dynamic approaches to verification performed at the C++ or SystemC HLS level of abstraction.
Hardware Accelerators – Exploring Power and Performance in Today’s AI
This session explores the design process from algorithm to hardware accelerator on a RISC-V processor as we quantify power consumption and performance.
Nokia: Experience in Adopting HLS and HLV Methodology
For increasing requirements for shorter time to market, Nokia has explored is raising abstraction level in both RTL design and verification with the help of High-Level Synthesis and Verification tools.
STMicroelectronics: In sensor Bricks Multi-objective Optimization of an Algorithm Chain for In-Sensor Processing
Through HLS and their innovative modular system, STMicroelectronics leads in the seamless integration of digital intelligence into analog native products, setting new standards for efficiency and market.
INOVA Semiconductors and Coseda: Paradigm Shift in Mixed Signal ASIC Design, Adopting SystemC and High-Level-Synthesis vs. Traditional RTL Design Flow
The authors will present the ease of use and the value-add of the HLS methodology in an automotive context.
HW Acceleration with High-Level Synthesis
Session introduces High-Level Synthesis, a technology that allows a developer to take a C++ function and automatically compile it into an RTL hardware description, suitable to be deployed into an ASIC or FPGA.
Fermilab: Bridging Machine Learning and Hardware Design with hls4ml and Catapult HLS
Fermilab introduces their partnership with Siemens to provide full integration with Catapult HLS design & verification flow, describe projects that have benefitted from hls4ml, and outline future directions.
Oak Ridge National Lab (ORNL): A Spiking Neural Network Architecture for Ultra-low Power and Ultra-low Latency Computing
ORNL with the help of the Siemens EDA tools, including Catapult HLS, the neuromorphic accelerator is being adapted from an FPGA prototype to a more capable and lower-power ASIC implementation.
How NVIDIA Uses High-Level Synthesis Tools for AI Hardware Accelerator Research
With constant change in AI/ML workloads, NVIDIA leverages a High-Level Synthesis design methodology based off SystemC and libraries like MatchLib to maximizing code reuse & minimizing design verification effort
.png?auto=format,compress?w=500&fit=max&q=60&dpr=1&auto=format)
Telechips: RTL Hardware Design Acceleration for On-The-Fly Image (De-)Warper in Automotive SoC Using C++ HLS
Telechips designed a new dewarping engine processing video stream data on-the-fly, different from traditional GPU-based memory-to-memory approach, by utilizing hierarchical design methodology in Catapult HLS.
STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP
STMicro presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) and a method to add constraints to the random values generated in UVMF.
Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc.
CEA: Bridging the Gap Between Neural Network Exploration and Hardware Implementation
CEA presents a methodology that bridges the open-source DL framework N2D2 and Catapult HLS to help reducing the design process of hardware accelerators, making it possible to keep pace with new AI algorithms.
High-Level Synthesis & Advanced RTL Power Optimization – Are you still missing out?
Discover how C++ & SystemC/MatchLib HLS is more than just converting SystemC to RTL. In the RTL Design space, we will cover our technology for Power Optimization with PowerPro Designer & Optimizer.
Infineon & Coseda: Facelifting a SystemC System Level Model Towards Physical Prototype – Adoption of High-Level-Synthesis
Infineon & Coseda present on the adoption of High-Level-Synthesis at an existing SystemC system level model.
Ultra Video Group (Tampere University): Managing the Complexity of an HEVC Encoder (Kvazaar) Implementation on FPGA with Catapult HLS
Dr. Panu Sjövall from Ultra Video Group (Tampere University), sheds light on how they were able to implement their embedded real-time HEVC intra encoder (Kvazaar) on HW with Catapult HLS.
Quantization of HLS Designs Using Value Range Analysis
Introduces simple & robust quantization methodology based on value range analysis. Learn what’s fixed-point conversion a.k.a quantization; dynamic & static quantization methods; and how to use Catapult VRA.
DUTh: Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators Using HLS
DUTh demos using HLS to design CNN accelerators with on-line checking capabilities, improve power efficiency due to optimized data handling on spatial variants of convolution, and effectively use HLS.
Alibaba: Innovating Agile Hardware Development with Catapult HLS
At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.
Cornell University: Building Sparse Linear Algebra Accelerators with HLS
Cornell intros HiSparse: accelerator on sparse-matrix dense-vector multiplication. Using both HLS implementation and simulation, their sparse accelerators deliver promising speedup.
FNAL: Ultrafast Neural Networks for On-Detector Edge Processing in Resource-Constrained Extreme Radiation Environment
FNAL demos that a NN autoencoder model can be implemented in a radiation-tolerant ASIC to perform lossy data compression. This alleviates the data transmission problem.
Harvard University: Effective SW/HW Co-Design of Specialized ML Accelerators Using Catapult HLS
Harvard sheds light on their agile algo-hw co-design & co-verification methodology powered by HLS. It led to an order of magnitude improvement in the design effort across 3 generations edge AI accelerator SoCs.
Stanford University: Edge ML Accelerator SoC Design Using Catapult HLS
Describes the design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the accelerator, and the integration of the accelerator into an SoC.
From Simulink to High-Quality RTL using High-Level Synthesis - The Design Methodology
Webinar introducing a design methodology starting from a flat floating-point Simulink model and step through to HLS generated RTL. All design steps including fixed-point conversion are described in detail.
From MATLAB® to High-Quality RTL Using High-Level Synthesis - The Design Methodology
Webinar introducing a design methodology that starts from a self-contained MATLAB script and goes through the different workflow steps to HLS generated, high-quality RTL. All design steps are detailed.
High-Level Verification of an AI/ML Accelerator Design
This webinar demonstrates how one can achieve comprehensive verification faster at a higher level of abstraction but still apply known and trusted RTL verification techniques.
HLS 101 - What Every RTL HW Design Team Needs to Know
High-Level Synthesis (HLS) extends the traditional design flow, providing a new and powerful approach to hardware design. It is important to understan
Microsoft - HLS Hardware Design Patterns
High-Level Synthesis (HLS) using untimed C++ presents an elegant hardware abstraction framework for simplifying hardware design at the unit level. To
Doing Research with Catapult HLS at Harvard
One of them is about proposing adaptive floating-point (FP) quantization to replace integer (INT) quantization for NNs.
NVIDIA: Design and Verification of a Machine Learning Accelerator SoC Using an Object-Oriented HLS-Based Design Flow
A high-productivity digital VLSI flow for designing complex SoCs is presented in this webinar. It includes High-Level Synthesis tools, an efficient im
Porting Vivado HLS Designs to Catapult HLS Platform
This webinar will cover how to port an existing HLS design developed within the Xilinx® Vivado® HLS environment into Siemens' Catapult® HLS Platform.
Early AXI4 SOC Performance Verification Using NVIDIA MatchLib and Catapult HLS
This webinar will introduce NVIDIA Matchlib and its usage with Catapult HLS using some AXI4 SOC demonstration examples.
From HLS Component to a Working Design
Complex algorithms do not exist in a vacuum. After High-Level Synthesis (HLS) is used to create an RTL component, to be useful, it needs to be integra
Part 1: Why Are High-Performance Low-Energy Applications Moving from GPUs and DSPs to FPGAs and ASICs?
Transistor counts and performance of integrated circuits are reaching their peak. Artificial intelligence is emerging as the next "big thing" in areas
Part 2: Adapting software algorithms to hardware architectures for high performance and low-power
GPUs and DSPs offer very high-parallelism and impressive memory bandwidths, within the scope of a fully programmable platform. However, they need to f
High-Level Verification: Verification Methodology and Flows When Using C++ and HLS
Highlights proven tools and methodology that help an HLS designer check and verify his design, measure, and close coverage, and compare the C to RTL implementation.
Building an iDCT for H.265 Using High-Level Synthesis
High-Level Synthesis (HLS), has been adopted by leading companies to speed design time and reduce verification costs in applications such as video and
Catapult HLS for RTL Teams - What You Need to Know
Catapult® HLS is a key competitive technology in several emerging markets like machine learning and vision. In this webinar, we cover both an introduc
Implementing Machine Learning Hardware Using High-Level Synthesis
Neural networks are typically developed and trained in a high-performance 32-bit floating-point compute environment. But, in many cases a custom hardw
Using high-level synthesis to accelerate computer/machine Vision applications
High-Level Synthesis (HLS) has been used in multiple companies, projects, and designs targeting vision processing for the past several years. HLS adop
Using HLS to Accelerate Computer Vision for Autonomous Drive
The algorithms to teach a computer to see, understand and make decisions for ADAS and Autonomous Drive systems require a significant amount of paralle
Stanford/AMD: Automated Methodology for Efficient Hardware Accelerator
Mobile devices today are composed of many specialized accelerators to achieve high-performance and low-power specifications. However, accelerator desi
Machine Learning: How HLS Can Be Used to Quickly Create FPGA/ASIC HW for a Neural Network Inference Solution
This session reviews the consideration around fast HW prototyping for validating acceleration in Neural Networks for Inferencing vs highest performance implementation and the tradeoffs.
Neural Network Quantization for Low-Power
This webinar will describe how to use Qkeras and High-Level Synthesis to produce a bespoke quantized CNN accelerator, and compares the accuracy, power, performance, and area of different quantizations.
Moving Between FPGA and ASIC with High-Level Synthesis
Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-indepe
Solutions for the Design and Verification of 5G SoCs
Catapult, Veloce 5G Fronthaul, Veloce X-STEP, Questa