Tessent Multi-die enables fully automated implementation of DFT for designs that scale sideways (2.5D devices), are stacked on top of one another (3D), or combine both configurations. The architecture for each die can stay independent regardless of what logic needs to be tested within or across the dies. Tessent Multi-die works seamlessly with Tessent Streaming Scan Network and Tessent IJTAG software, which optimize DFT test resources for each block without concern for impacts to the rest of the design. This effort dramatically streamlines DFT planning and implementation for the 2.5D and 3D IC era. Using Tessent Multi-die, IC design teams can rapidly generate IEEE 1838-compliant hardware featuring 2.5D and 3D IC architectures. Tessent Multi-die is the industry’s first way for DFT to be used for 2.5D/3D in collaboration with packetized scan data approaches where access to each die versus the device is effortless.