Hossam Sarhan, a senior Calibre product engineer, introduces viewers to Calibre PERC packaged checks. Packaged checks offer pre-coded verification solutions that users can easily select, configure, and deploy across various design and verification flows.
Sarhan highlights the versatility of packaged checks, showcasing examples including analog layout checks, ESD checks, IO ring checks, and voltage-aware DRC checks. He explains how analog constraints packaged checks enable designers to apply check constraints such as symmetry and device match to specific device groups, simplifying analog layout verification.
Furthermore, Sarhan discusses ESD packaged checks, which verify the existence and integrity of ESD devices and interconnects, and IO ring packaged checks, which ensure proper IO placements and ESD distributed schemes. He emphasizes the user-configurability of packaged checks, facilitated by a graphical user interface that allows easy creation and configuration of check constraints.
In conclusion, Sarhan underscores the role of packaged checks in simplifying the adoption of Calibre PERC technology, empowering designers and non-experts to validate specific areas of their IC designs with ease. Packaged checks offer a streamlined approach to reliability verification, enhancing productivity and accelerating time-to-market for semiconductor products.