Introducing Calibre DesignEnhancer Calibre-clean layout optimization during design implementation

Design companies need EDA solutions that improve the robustness of their designs and shorten their time to market. The Calibre DesignEnhancer tool is part of our Shift Left with Calibre Solutions initiative. The Calibre DesignEnhancer use models automatically apply layout optimizations during design implementation to improve EMIR results and reduce design cycle time across all leading foundries and technologies. These push button, user-friendly use models employ proven Calibre analysis and rule decks to correctly modify the layout. The DRC clean results are then integrated back into the design flow using industry standards for additional ease of use.

Correct by construction layout optimization during IC design implementation

Whether you’re designing custom/analog ICs or implementing digital IC design layouts, the Calibre DesignEnhancer tool lets you apply automated, correct-by-construction layout optimizations to improve design reliability and power management while also speeding time to signoff verification and reducing time to market. By identifying and resolving issues earlier in the design flow with signoff-quality solutions, the Calibre DesignEnhancer tool enables you to compress cycle time while increasing design quality.