Low-power design requires continuous effort at every stage of RTL design. From early RTL IP to stable SOC, it is essential to provide feedback on power and factor changes into RTL revisions to make sure that the RTL consumes less power. However, the available options to design-for-low-power depend on the design stages. This session will explain how a design methodology can be established that helps find power issues throughout the RTL design cycle and provide continuous feedback to RTL designers to enable development of low-power energy efficient chips.