Google reduces power grid IR drop issues during P&R with automated analysis-based layout enhancements
Automated DRC-clean layout optimization during IC design implementation reduces IR drop for fast, effective power management
Google was looking for a fast and easy way to reduce IR drop violations by applying DRC-clean layout enhancements to their design during the design implementation stage. They turned to the Calibre DesignEnhancer tool from Siemens EDA, an automated, analysis-based layout optimization solution designed to be used in conjunction with P&R tools and flows. The Calibre DesignEnhancer tool provides multiple layout enhancement technologies that help reduce IR drop without negatively impacting performance and area. The user-friendly push-button operation requires minimal training and setup, and because the Calibre DesignEnhancer software relies on Calibre engines and Calibre rule decks, all layout modifications are correct by construction and DRC-clean.