Finding and fixing leakage between power domains

Current leakage between power domains is a critical challenge in modern semiconductor design, as chips become more complex and include multiple independent power rails. Traditional electrical rule checking (ERC) methods generate numerous false positives, making leakage analysis inefficient and unreliable. This paper examines the complexities of power domains and introduces a two-stage approach—first, finding all potential leakage paths; then, applying advanced filtering to isolate genuine risks. The Siemens EDA’s Insight Analyzer tool streamlines this process, using context-aware logic to detect, filter and present actionable results so designers can accelerate debug and ensuring higher-quality, robust silicon products.

What you'll learn:

• Why inter-domain leakage is a critical reliability concern.
• The unique challenges of analyzing power domains.
• How to methodically detect and triage leakage issues.
• How the Insight Analyzer tool improves detection and debug.

Who should read this:

• IC circuit designers and verification engineers, especially those working on low-power, mixed-voltage or multi-domain chips.
• EDA tool users and CAD engineers responsible for design reliability, ERC methodology or power intent.
• Managers and technical leads in semiconductor design and verification.