Accelerating advanced-node ramp up and robust design enablement for leading edge SoC designers

A key challenge for advanced process node ramp-up and design enablement is the lack of quality and comprehensive layout that can effectively probe process capabilities and design/process interaction.

Comprehensive test cases are required to evaluate process quality, printability and performance. These test cases are also required by design enablement teams to calibrate, develop and validate technology process design kits (PDKs) that enable SoC engineers to design and validate IC products.

Random synthetic layout generation closes the time to resolving these issues. We generate the requisite layouts for test-chip development, silicon measurement, process development, design tool PDK development and production design enablement.

The Calibre Layout Schema Generator (LSG) tool generates synthetic layouts, providing comprehensive pattern coverage and stress pattern coverage of the vast design space. This lets engineers detect and correct problems earlier and delivers a robust technology node and an accurate design enablement flow to leading edge SoC designers.