Questa Signoff CDC verification

Questa Signoff CDC uses automated, advanced structural analysis algorithms optimized for gate-level analysis, as well as automated leveraging of waiver and CDC path information from Questa CDC RTL analysis for exacting, “low noise” results. It then illustrates the DUT issues found with familiar schematic and wave-form displays. As with RTL CDC verification, these issues cannot be detected by any other method, including simulation and static timing analysis.

New Risks from 28 nm Nodes and Below

Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has more than one clock domain (i.e., 99% of all designs today) does not accurately model the silicon behavior related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon functionality; thus show-stopper bugs will escape. Even worse, as the available “bandwidth” at the 28 nm node and below decreases, RTL-to-gate synthesis can create glitches and CDC issues that are unobservable by CDC analysis at the RTL.

Specifically, RTL synthesis can break corrective circuitry; i.e., break-up “synchronizers” added into the RTL to remove CDC issues between groups of signals that are generated in one clock domain and consumed in another. RTL synthesis can also improperly implement related combinational logic and introduce disruptive glitches. Bottom-line: at 28 nm and below, without RTL and gate-level CDC analysis, CDC bugs will only be discovered in the lab when it is too late and a respin will be required.