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Hewlett Packard Enterprise: Standard cell and memory .lib production and verification using machine learning

The methodology for producing and verifying new PVT .libs for standard cells and memories.
The methodology used for producing and verifying the full set of PVTs consists of Solido Generator for producing new PVT .libs and Solido Analytics for .lib verification. Both are part of Siemens EDA’s Solido Characterization Suite.

For 7nm designs, timing libraries (.libs) require characterization over a large number of process, voltage, and temperature (PVT) corners to provide adequate coverage for digital design and sign-off, as well

The Solido Characterization Suite from Siemens EDA helps the design teams at Hewlett Packard Enterprise (HPE) achieve faster time-to-market. They accomplish this by providing a machine learning (ML)-enabled solution to produce and verify new PVT .libs for memories and standard cells significantly faster than SPICE characterization, saving weeks of production schedule time.

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