A scalable end-to-end solution for RISC-V debug and trace

As software design complexity increases, so do the time, effort, and costs associated with debugging and optimizing applications on multi-core System-on-Chips (SoCs). More efficient methods are needed to identify hardware and real-time software issues. This white paper describes Tessent UltraSight-V, a RISC-V debug and trace solution that follows the official RISC-V E-Trace specification. It combines embedded hardware IP and software to accelerate time to market, offering modular design and minimally invasive logging for efficient troubleshooting. This solution can identify and resolve errors faster than traditional software-only methods.