Accelerating AMS verification with Mixed-Signal Visualizer

Debugging now consumes approximately 47 percent of integrated circuit (IC) verification time due to increasing semiconductor design complexity. Analog mixed-signal (AMS) verification presents unique challenges, as engineers must correlate continuous analog behavior with discrete digital logic across multiple abstraction levels, hierarchical configurations, and voltage domains.

Traditional waveform-based debug tools are insufficient for modern AMS verification, resulting in poor observability and inefficient workflows. Engineers require a unified solution capable of handling multiple modeling formats, complex boundary element (BE) configurations and industry-standard methodologies like the Unified Power Format (UPF) and the Universal Verification Methodology (UVM).

Siemens EDA's Symphony Pro with Mixed-Signal Visualizer (MS Visualizer) addresses these challenges through a comprehensive graphical debug environment featuring multi-window design visualization, automatic schematic generation, mixed-signal net analysis, boundary element inspection, and logic cone tracing.

Real-world case studies demonstrate MS Visualizer's effectiveness in diagnosing complex issues, such as multiple-driver scenarios and boundary element configuration errors. Symphony Pro with MS Visualizer reduces verification time, accelerates issue resolution, and helps teams deliver designs to market faster.

Symphony Pro Mixed-Signal Visualizer

Siemens EDA's Symphony™ part of Solido™ Simulation Suite, is a highly configurable mixed-signal technology designed to accurately verify design functionality, connectivity, and performance across analog/digital interfaces at all levels of the design hierarchy and for all IC applications. Symphony Pro is the advanced tier of Symphony and an all-Siemens solution that works with all Siemens analog solvers plus the Questa™ digital simulator, the industry-leading, high-performance, multiple-language digital simulator. Symphony Pro can support any combination of analog blocks described in SPICE syntax, digital blocks described in HDL languages (Verilog, VHDL) and AMS behavioral models (Verilog-AMS, VHDL-AMS, VerilogA). It produces rich mixedsignal simulation data that can be explored using the Mixed-Signal Visualizer also known as “MS Visualizer” - a comprehensive graphical debug environment. MS Visualizer offers a seamless debug experience across the entire mixed-signal design hierarchy with comprehensive analysis, automation, and ease-of-use.