Timing intent and structural exceptions validation with SVA’s in functional simulation

Authoring and validation of timing exceptions has always been a challenge for both front-end and back-end engineers. Today, generally such validation takes place manually, and it happens at various takes of the design depending on the requirements for each stage of design and implementation.

A typical timing constraint for a given design contains description of timing behavior of the Clocks, their interactions, the IO interface timing and most importantly, the timing exceptions.