Qualcomm: Designing ASIC IP at a higher level of abstraction

Qualcomm has successfully applied their HLS/HLV flow and Siemens EDA’s HLS/HLV technology on a wide range of video and image processing IP designs including IPs which were integrated into their flagship smartphone applications. Proving the usefulness of HLS/HLV across many design styles, these IP blocks range in size and complexity from small and simple to large and complex; from small data bandwidth compression blocks, with tight feedback loops, instantiated in many places on a chip to large subsystems implementing very complicated logic.

In order for HLS/HLV adoption to be possible, standardized corporate design flows for HLS coding style, linting, constraint-driven synthesis, and design build as well as structural and functional verification of C++ and SystemC code were required. This paper discusses some of the reasons why this new HLS/HLV flow gives companies like Qualcomm several advantages, summarizes the flow and its benefits, and describes how it can provide even more advantageous features in the near future.