Power optimization of a configurable video platform using PowerPro

This paper will demonstrate the application of PowerPro® and SLEC® to reduce power on the ARC® AV 401 video platform. Based on the methodology used and the results achieved, it will become obvious that this same methodology could be applied by designers to other ARC products generated by the ARChitect™ tool including the ARC® Sound 210 Subsystem, ARC® 600 Series, and ARC® 700 Series.

Introduction to video power optimization technique

With the proliferation of mobile multimedia devices, designers are challenged to provide the most advanced features to users while balancing the need to deliver the longest battery life possible. Maintaining this balance has been a significant challenge for designers, with no automated solutions available to ensure the lowest power solution is achieved. One way to reduce power and extend battery life is to reduce the amount of switching activity in the device. Understanding how the silicon works in normal use can help direct subsystem design changes to eliminate unnecessary switching activity without sacrificing leading edge functionality and performance. Once identified, the challenge is to quickly and efficiently implement the changes in the RTL and be able to verify that the functionality has not been affected by the changes.

Today, most ICs designs include the integration of newly designed circuitry, legacy circuitry available from a previous design generation, and 3rd party IP. Realizing the lowest power design while integrating legacy circuitry and 3rd party IP is extremely difficult. Without the detailed knowledge of how the RTL works, most designers choose to concentrate their efforts on optimizing power on the newly designed circuitry, ignoring the additional power savings that could be achieved on the other portions of the design.

Clock gating is one common Register Transfer Level (RTL) power optimization technique that reduces design switching activity. It relies on the ability of synthesis tools to identify certain RTL structures and convert those structures into simple combinational clock gating logic. Until recently, inserting these structures into RTL was a tedious, error-prone, manual process. Verification of the structures required the creation of new test benches to ensure that the changes to the design did not affect functionality. With the advent of RTL power optimization and verification tools, the process has become automated, providing an ideal solution for reducing power in highly configurable SoC subsystems used in today＊s mobile multimedia devices. 

PowerPro® can automatically insert advanced sequential clock gating structures into an RTL design. It is based on Siemens EDA, a part of Siemens Digital Industries Software＊s patented Sequential Analysis Technology, and is proven to reduce power by up to 60% on customer designs. PowerPro clock gating evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions and generates new RTL which is identical to the original RTL with new clock gating enable logic inserted. All user defined pragmas, indentations, comments, etc. are maintained. Designers feel comfortable with the generated RTL because they can still recognize their original coding style and are provided direct insight into the logic inserted by PowerPro. PowerPro does not rely on the users knowledge of the RTL design. Because PowerPro automatically analyzes sequential behavior without the need for design knowledge to be presented to the tool, users can easily achieve excellent power optimization results on any design block run though the tool even if they are unfamiliar with the details of the RTL. PowerPro, therefore, is a perfect solution for delivering the lowest power design where 3rd party IP is being integrated into an IC. 

SLEC® is a sequential equivalence checker that provides efficient, comprehensive verification of the PowerPro generated RTL. SLEC formally compares the functionality of the original RTL design with the PowerPro optimized RTL design for all possible input sequences to ensure functionality has not been compromised.