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White Paper

Post-layout simulation is becoming the bottleneck for analog verification

Analog FastSPICE and AFS eXTreme are the answer for removing analog verification impediments

The FinFET 3D structure has driven an explosion in the number of computations required per device. This contributes to more expensive model evaluation and longer simulation times.
FinFET 3D structure.
Significantly faster than any other SPICE-accurate simulator on a single-core, AFS also employs multithreading for scalable performance improvements for long runs. Its device noise analysis delivers silicon-accurate results with simulated results within one to two decibels (dBs) of measured silicon. And with its greater than 100M element capacity, AFS eXTreme enables verification of full circuits with detailed parasitics for the most advanced process geometries, removing the analog verification bottleneck with no accuracy loss.

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