relatório técnico

Curvilinear MRC with GPU-native Calibre

Scalable, high-throughput curvilinear mask verification for modern semiconductor production flows

Bar chart comparing CPU and GPU runtimes for different accuracy specifications in dbu. For all specifications, GPU time is significantly lower than CPU time.

Semiconductor manufacturing is undergoing a major transformation at advanced nodes, where tight pitches and complex geometries demand the adoption of curvilinear masks and cubic Bezier splines. However, the shift toward these new geometries introduces dramatic computational bottlenecks in optical proximity correction (OPC) workflows, particularly in the mask rule check (MRC) phase. Traditional CPU-based methods are increasingly unable to keep pace with the throughput and accuracy requirements of high-volume production, resulting in escalating costs and potential manufacturing delays.

Siemens Digital Industries Software has responded to these challenges by developing a GPU-native MRC solution, seamlessly integrated into Calibre OPC flows. By reengineering the measurement algorithms for Bezier curve geometry and leveraging massive GPU parallelism, the new workflow achieves up to 37x speedup versus conventional approaches, with an order-of-magnitude improvement in measurement accuracy. This white paper details the technical breakthroughs, deployment strategies and business impacts of the GPU-accelerated MRC flow, illustrating how it empowers foundries, design teams and IT organizations to unlock the full potential of curvilinear mask production.

What you’ll learn:

  • How GPU acceleration overcomes the computational bottlenecks of curvilinear OPC mask rule checking.
  • The proven runtime, accuracy, and memory improvements for high-volume semiconductor manufacturing.
  • Best practices for integrating GPU-based flows into existing Calibre OPC workflows.

Who should read this:

  • IC design engineers and mask data prep teams
  • DFM and manufacturing process engineers
  • Technical managers and CAD/flow architects
  • Semiconductor foundry operations teams
  • IT specialists supporting EDA and HPC infrastructure

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