From chiplets to signoff: Capturing cross-die coupling in 3DIC parasitic extraction

Advanced 2.5D and 3D integrated-circuit (IC) architectures are enabling a new generation of high-bandwidth, high-performance and heterogeneous semiconductor systems. By integrating logic, memory, analog, RF and package-level interconnect in close physical proximity, 3D IC technologies can deliver significant system benefits. However, the same physical proximity that improves performance also introduces new parasitic interactions across die interfaces, interposers, package redistribution layers, TSVs (through-silicon vias), hybrid bonding regions and back-side metal stacks. These interactions must be modeled with sufficient accuracy to support reliable timing closure, signal-integrity analysis, power-integrity analysis and system-level simulation.

This paper focuses on interface extraction for 3D IC parasitic extraction flows. It describes why cross-die capacitive coupling becomes important in tightly bonded stacks, how Calibre-based flows address standalone die extraction and interface extraction and how generated interface parasitics can be combined with component parasitics for static timing analysis, dynamic simulation and signal-integrity analysis. Finally, it highlights a new capability: extraction of coupling capacitance for fractured nets, including internal nets, by automatically introducing connection points that allow cross-die coupling capacitors to be represented correctly in the 3D IC netlist.

What you'll learn:

• The importance of cross-die capacitive coupling in 3D IC architectures
• How Calibre-based flows address standalone die extraction and interface extraction
• How to combine standalone die parasitics and interface parasitics for system-level simulation
• A new capability for extracting coupling capacitance for fractured and internal nets

Who should read this:

• Design engineers working with 3D IC architectures
• Verification engineers performing timing closure and signal integrity analysis
• System architects integrating heterogeneous components in 3D IC systems
• Anyone interested in advanced 3D IC parasitic extraction methodologies