A method to eliminate the need for functional gate level simulations

Traditionally, the RTL simulations are followed by gate level simulations (GLS) in order to catch issues that may not exist at the RTL level. Such issues maybe to check for structures such as DFT logic that was added afterwards. However, another major reason for running GLS, is to check the validity of timing constraints as specified in the SDC file. Even though, there are rule based static constraints verification tools, they cannot validate the intention of the timing values as specified by the designers.

Since, setting of the GLS is very arduous and iterative task, it is often limited on validating only a subset of tests.

This paper presents an assertion-based verification (ABV) methodology that uses the System Verilog Assertions (SVAs) to validate the timing constraints specified in the SDC file.