As design nodes shrink, the design and manufacturing complexity has dramatically increased along with systematic defects. The result is a slowing of the yield learning curve as wafer defectivity grows. Calibre can help accelerate the yield enhancement process and streamline DFM/OPC with full-flow design-guided analysis facilitated by machine learning techniques.
The current work flow for analyzing systematic defects in the fab involves design profiling and layout decomposition, grouping regions by design geometry properties using Calibre DRC and Calibre Pattern Matching. These "care areas" are then fed to inspection tools like e-beam metrology or bright-field inspection.
The amount of potential defect data generated can be unwieldy, but a down selection based on design geometry analysis reduces the amount of data for the scanning electron microscope (SEM) review. Once the SEM review is done, fab engineers can do SEM images layout analysis like SEM-to-layout alignment, defect classification, and contour extraction. These analyses are done using Calibre DefectClassify.
Once the defects are classified, the engineers still need to find the root cause. The Calibre DefectReview interface is used for design-guided defect root cause analysis and process failure analysis. Once root causes are identified, those weak patterns can go into the process library and be used for building defect databases and OPC silicon correction and verification. Ultimately, it's fed into the new product design rules.
The enhanced work flow presented in this video using machine learning techniques in Calibre SONR to improved pattern detection and clustering. Calibre SONR is inserted into the current flow during the generation of 'care areas' from the design layout, and again during the SEM down sampling. Also, a full-chip prediction by Calibre SONR provides a useful supplement to the defect locations reported by bright-field inspection as input to SEM review. Finally, Calibre SONR can be used to retrain and fine tune the defect database models. Using design information and machine learning techniques enhances inline defect signal extraction and root cause analysis, driving yield improvement.
About the presenter:
Qian Xie, Siemens Digital Industries Software, Product engineer
Qian is a product engineer at Siemens EDA, focusing on defect management and fab analytic products. Her primary focus in inline defect and metrology fields, especially on new methodology development that uses design analysis to improve defect signal extraction on/off hardware tools, increasing data analysis efficiency to drive yield improvement.