Bringing 2.5D verification into the design process

Microsoft completed a complex 2.5D design comprised of an in-house developed SoC, Third Party IP, a silicon interposer and an organic package substrate. Microsoft had previously worked with Siemens and deployed Xpedition Substrate Integrator (XSI) and Calibre 3DStack for 2.5D LVS verification. For this design Microsoft again wanted to perform 2.5D LVS and DRC verification but wanted to start doing it earlier in the design cycle as opposed to waiting for until all the pieces were complete or close to tapeout to run the 2.5D verification flow. Over the course of the project, 2.5D verification, both LVS and alignment DRC checks, were run on a regular basis to support the design teams through the design iterations and successful tapeout. Additionally, several new checks were developed specifically to identify design issues the team was concerned about. This presentation will describe how Microsoft used Siemens 3D IC verification solutions to help address design problems as well as verification of the full 2.5D system.

Some of the highlights of the project were:

• Early detection of an interposer to package alignment problem
• An innovative methodology to quickly validate the package to interposer interface
• Full system LVS including 1200+ net naming changes between package and interposer
• Detection of ""Power Islands"" on nets which should have been fully connected
• A solution to resolve inconsistent bump naming in third party IP resulting in LVS failures
• Introduction of Calibre PERC driven from XSI to perform selected P2P resistance checks on the interposer

Authored by:

• Olga Calderon, Microsoft
• Ram Kadiyala, Microsoft
• Gurupada Mandal, Microsoft
• Tarek Ramadan, Siemens
• Russ Stauffer, Microsoft
• Michael Walsh, Siemens