System-level, post-layout electrical analysis for high-density advanced packaging

As HDAP designs like fan-out wafer-level packaging (FOWLP) become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. We provide an accurate, automated flow that generates the required HDAP netlist for simulation/STA to enable HDAP designers to ensure that the HDAP will perform as designed.

For more information on Package Simulation, please click here.