Faster short isolation with LVS Recon runs in Calibre RVE

Increases in design size and complexity at current technology nodes cause early and dirty designs to generate millions of LVS violations, which leads to longer layout versus schematic (LVS) runtimes and debugging cycles. This makes ensuring fast LVS turnaround time in early design cycles more challenging. Designers tackle this by prioritizing the most critical violations first. Therefore, developing a robust verification flow with efficient design-stage analysis and debugging capabilities for critical connectivity checks can make a significant difference in achieving faster system-on-chip (SoC) circuit verification.

In this paper, we discuss key challenges designers face during LVS verification cycles, focused on debugging one of most critical violations – the shorted nets. We then highlight how the enhanced integration of the Calibre nmLVS Recon graphical user interface (GUI) within the Calibre Results Viewing Environment (RVE) can help designers improve the LVS process.

What you'll learn:

• How context shifting between tool environments impedes the verification process
• Reduce debugging efforts by identifying and addressing issues earlier in the design flow
• Use the familiar Calibre RVE to launch the Calibre nmLVS Recon GUI
• Increase productivity of the interactive shorts isolation process

“When you run LVS the first time at the large block level, the whole thing lights up with circuit errors that you have to go fix. The problem is that you have to wait for the entire overnight run to finish before starting to fix all those shorts. That's where the Calibre nmLVS Recon tools help. You get Calibre signoff accuracy, but 10X faster." – Joe Sawicki

Who should read this:

• Circuit verification engineers and IC designers seeking to improve their interactive short isolation process
• IC and SoC designers interested in the latest advancements in semiconductor design