Extraction challenges of CFET and backside power delivery

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive performance for AI accelerators, data centers, and mobile processors but present new extraction challenges in accurately modeling parasitic resistance and capacitance. Siemens Calibre xACT provides unified extraction tools for both front and back metal stacks—enabling precise simulation of TSV and non-Manhattan routing effects. The paper details how Calibre xACT supports workflow setup, interface resistance modeling, and RLCK extraction, positioning design teams for reliability, power efficiency, and success in next-generation device engineering.

What you’ll learn:

• How CFETs and BPRs advance device density and power efficiency in semiconductor nodes at 3nm and below
• Technical foundations for resistance, capacitance, TSVs, and non-Manhattan routing in IC extraction
• Workflow for setting up Calibre xACT and xCalibrate for accurate parasitic extraction
• How interface resistance and backside metal stack modeling improve reliability and performance
• Methods to simulate RLCK parameters and TSV coupling for robust design verification

Who should read this:

• Semiconductor process and device engineers
• IC CAD tool and EDA users
• Design verification and signoff engineers
• Advanced-node library and cell designers
• EMIR, reliability, and parasitic extraction specialists