Customize and standardize your IC verification configuration

The right mix of rule decks, inputs, variables, and operating conditions ensures designers optimize the accuracy and performance of their signoff verification flows. Creating a configuration setup manually is time-consuming and error-prone. To increase designer productivity, EDA companies developed interface tools that enable design teams to quickly and accurately set up methodologies that are automated, repeatable solutions integrated into their design and verification tools.

Optimizing signoff physical verification run configurations with Calibre interfaces

Considering the number of Calibre verification runs designers launch in a tapeout cycle, even modest gains in efficiency can represent significant gains in productivity. By enabling the creation of run configurations in a consistent, easy-to-use visual environment, Calibre interface tools eliminate multiple time-intensive manual tasks, freeing up more time for designers to focus on meeting design goals and tapeout schedules. The Calibre toolsuite provides several interface tools, including the Calibre Interactive invocation GUI, the Calibre RVE results viewer, and the Calibre DESIGNrev chip finishing interface, that enable designers to manage these tasks easily and accurately.