Advanced electrical rule checking in IC reliability verification

Electrical rule checking verifies the robustness of a schematic or layout design, ensuring that circuits will operate as designed and intended. ERC violations can result in reduced yield and/or potential circuit malfunction or electrical failure after product delivery. With its logic-driven layout framework, automated voltage propagation, and the ability to combine physical and electrical information to determine context, the Calibre® PERC™ platform enables automated sign-off quality verification for today’s most complex ERC at various design stages, including IP, block, and full-chip levels.

Advanced electrical rule checking is essential to IC design reliability and performance

Without a full set of advanced electrical rule checks, companies risk releasing products that do not perform as designed, or experience premature failure in the field. To implement these checks, electrical verification tools must now understand complex connectivity and device information, including circuit recognition. With its ability to combine electrical and physical attributes, the Calibre PERC reliability platform provides advanced circuit verification for ESD, EOS, multiple power domains, advanced ERC, and other reliability concerns. By enabling context-aware signoff verification for today’s most challenging electrical design rules, the Calibre PERC reliability platform empowers design companies to deliver reliable, robust IC products that provide the performance and product life the market demands, on schedule and on budget.