Streamlining 3D IC design: Finalizing substrate design for fabrication

In eBook number five, we discussed the finalization of the power delivery network (PDN) structures to ensure that adequate and stable power is available to the chiplets and over devices during operation. With that completed, the designer pivots focus to ensure that the PDN is optimized and in-line with the fabrication process to ensure yield and reliability.

PDNs are typically constructed as large metal filled areas, sometimes referred to a metal pours. Such large areas can cause fabrication issues – such as outgassing, where gas bubbles (formed during the manufacturing process between the package layers) try to escape, introducing the risk of layer delamination and substrate warping. The standard approach to mitigate this risk is to insert degassing voids in the metal areas. The substrate fabricator will typically provide rules for the voids, which are often

varied in size as well as shape and are inserted in areas above a certain size. This can be a tedious process unless you are using a dedicated substrate / interposer design tool such as Innovator3D IC™ Layout software.