Taking AI neural processing unit design into the future

Introduction

The Electronics and Telecommunications Research Institute (ETRI) is a government research institute that focuses on IT and semiconductor components. In 2019, the PIM AI Semiconductor Research Group at ETRI’s National AI Research Institute developed the first Korean AI processor, called AB9.

With the goal of designing the next generation of ultra high-performance AI neural processing unit (NPU), the ETRI Design Group leveraged 3D IC packaging technology to develop a chiplet AI processor that integrates multiple AI NPUs with eight HBM3 high-bandwidth memory stacks. This new highly-advanced chiplet-based AI NPU is called ABS1, which takes advantage of 3D IC packaging’s ability to dramatically increase bandwidth and performance while reducing the power and cost of highly-complex, high-performance ASIC designs.

These chiplet architectures provide the increased compute power, memory access, and storage that ETRI’s AI processors require. Employing this truly groundbreaking chiplet technology, ETRI is equipped to create next-generation, ultra-performance AI NPUs.

The ABS1 chiplet is the first energy-efficient petaflops-class AI processor. One petaflop is equivalent to 1000 teraflops, which delivers the performance of 10,000 application processors combined into a single AI processor. ABS1 features Amkor’s redistribution layer (RDL) interposer, which uses a large-scale substrate.

The ABS1 NPU being designed in Xpedition Package Designer by the Amkor advanced IC packaging design team.

The right tools to get a tough job done

Due to the long, successful relationship between Amkor and Siemens leveraging the quality and capabilities of the Siemens’ advanced packaging solutions, Amkor and ETRI selected Xpedition™ Package Designer (xPD), Innovator3D IC™ (i3D), and Calibre® 3DSTACK, all from Siemens DISW, to help them establish a systematic approach for designing their chiplet-based AI NPUs.

Amkor Korea Design Team utilized i3D for connectivity, XPD for physical layout and Calibre for verification because of its excellent design and verification capacity and performance, which Amkor needed to verify S-SWIFT designs including the RDL interposer. Amkor Korea chose xPD for RDL interposer design because it contains specific functionalities and is compatible with top die bumps and RDL interposers, streamlining the design flow. Amkor was able to integrate 3DSTACK level design structures through i3D for both the RDL interposer and the PCB substrate.

The Amkor team was motivated to perform NPU and HBM connectivity optimization for the RDL interposer design, which was successfully completed by collaborating with ERTI using i3D. Amkor also needed to verify connectivity of S-SWIFT for top dies and RDL interposers as well as the package substrate. Amkor used Calibre 3DSTACK verification on the S-SWIFT advanced package designs. They also adopted xPD for this multi-layer substrate RDL interposers and S-SWIFT designs. For DFM, Amkor used Calibre for final sign-off.

Amkor has experience using i3D for bump connection visualization and optimization during multi-die integration. i3D has proven to show exceptional design capacity even when dealing with bump counts in the hundreds of thousands.

The ABS1 NPU shown being prototyped and floorplanning in Innovator3D IC by the Amkor advanced IC packaging design team.

Amkor had a history of success running Calibre 3DSTACK verification for high-density advanced package designs, so they thought it was a good choice for ETRI’s AI NPU processor project. i3D is packed with features that enable Amkor to integrate 3DSTACK level design structures for both the RDL interposer and the package substrate. i3D can handily perform the bump connection optimizations required to achieve a high quality RDL interposer design, which was successfully done by using i3D on the interposer.

ETRI adopted i3D for interposer floorplanning of the NPU die and HBM die. It is their main solution for visualizing bump-to-bump connections as well as micro-bump-to-C4 bump connections, including package BGAs. This is a much more efficient process than their previous approach, which used only Verilog netlists. ETRI was required to take sign-off 3DSTACK verification for both the interposer and package, so Siemens supported the final assembly verification with i3D, xPD, and Calibre 3DSTACK for the interposer and package substrates.

ETRI is focused on building seamless VLSI CAD flows for advanced packaging. Innovator3D IC provide an intuitive understanding of the chiplet architecture of ABS1 with multi-die, chiplet, and HBM3 stacks. By describing the top-level chiplet architecture, i3D can be used to seamlessly move into xPD’s interposer and package substrate design and architecture simulation tool environments.

Minseok Choi, the principal researcher in charge of the ETRI AI SoC Research Division, recalls, “We successfully integrated a seamless chiplet VLSI CAD design flow with i3D and developed a systematic approach to designing chiplet-based chips using i3D.”

The ABS1 NPU shown in Calibre 3DSTACK/DesignRev where final assembly verification/signoff is performed.

Solutions for next generation of semiconductor architectures

Jinho Han, Ph.D looks beyond this successful collaboration with great optimism. “Siemens’ initiative to provide a CAD design environment for interposer and package substrates for advanced packaging has laid a foundational work for architecture designers. We expect Siemens to further enhance the i3D environment to meet the design criteria for chiplets, which are considered the next generation of semiconductor architectures.”

TaeKyeong Hwang, Ph.D, product development division manager at Amkor Korea concludes, “We are pleased to work with Siemens, which continues to improve Amkor EDA systems by offering more features supporting our seamless advanced package design flow. Package design complexity has grown to include advanced architecture, hundreds of thousands of connections, and complex implementations. Amkor and Siemens continue to collaborate to make better i3D and Calibre 3Dstack environments to align with our customers, focusing on RDL interposer and substrate design in advanced packaging for today and for the next-generation.”

The ABS1B device is the chiplet-based chip. and, The final ABS1A device will be the first petaflops AI processor with very high energy efficiency.