UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and Now UPF 3.1: which is right for my design

UPF is the fastest evolving IEEE standard, and UPF 3.1 is a major milestone in its evolution. This paper provides an in-depth analysis and relevant examples of all the new features introduced in UPF 3.1 along with semantic differences with earlier versions. It also highlights migration challenges to help users migrate from existing power formats to UPF 3.1.

The increasing complexity and growing demand for energy efficient electronic systems has resulted in sophisticated power management architectures. To keep up with the pace, the IEEE 1801 standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs. With the recent release of the IEEE 1801-2018 (UPF 3.1), several new features have been added along with improving clarity on existing features.

With this, we have five UPF standards posing some questions about the compatibility, differences, and challenges related to migration and its impact on verification. For any low-power designer the big question arises which is the right standard for my design. In this paper, firstly we will provide an in-depth analysis and relevant examples of all the new features introduced by the UPF 3.1 along with highlighting any semantics differences with the earlier versions. The paper will include detailed analysis of broader topics which have been semantically changed over the UPF versions.

Power management and verification complexity

The growing demand for energy efficient electronic systems has resulted in sophisticated power management architectures. The constant need to minimize energy consumption to increase battery life for portable devices, and reduce heat dissipation for non-portable devices to minimize cooling costs ensure that power management is critical part of any electronics designs.

Designers employ a variety of advanced techniques ranging from clock gating and power gating to multiple voltages and dynamic scaling of voltages and frequency. If not executed correctly, these techniques can affect the functionality of the design. Hence, it becomes important to verify the power management to ensure functional correctness of designs. The power management consideration starts as early as the system design phase to achieve maximum benefits and it gets further refined at

various phases of the design cycle. It is important to verify the power management at every stage in the design flow so that any functional bugs are rectified.

The application of power management results in the modification of the original design and insertion of special power management structures like isolation, level shifters, retention, etc. at various places in the design. Due to the complex interaction of these structures with the normal design functionality, it poses a serious of challenge to verification. To add to it, the various IPs with their own power management need proper verification to remove any integration issues related to power management.

To aid the verification process, power intent specification formats can share the burden by defining clear and consistent semantics enabling tools to automate various tasks related to power management.