Artykuł techniczny

11 myths about hardware-assisted verification

EDA expert Dr. Lauro Rizzatti debunks the myths surrounding the two tool classes of HAV platforms - hardware emulators and FPGA prototypes

HAV platforms include emulation and prototyping deployed in physical and virtual mode. In virtual mode, a comprehensive test environment supported by virtual peripherals mimics the behavior of the physical target system where the SoC will be plugged in.
EDA expert Dr Lauro Rizzatti of Siemens EDA debunks the myths surrounding the two tool classes of HAV platforms - hardware emulators and FPGA prototypes - in this Electronic Design exclusive.

Emulators verify hardware and integrate hardware and software of any size and type of system-on-chip (SoC) designs. They also can head start the validation of software and final system validation of the entire SoC.

By comparison, FPGA prototypes, running at an order of magnitude faster than emulators of the same design size, are ideal for software and final system validation ahead of silicon. They come in two basic configurations. One is the desktop board that serves single users with an upper limit in design capacity of about 100 million gates. Enterprise platforms supporting multiple concurrent users reaching a maximum capacity of over 10 billion gates is the other.

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