Every circuit board has resistance, capacitance, and inductance values associated with board traces. Board level parasitics can negatively affect circuit performance - while their values may be small, their cumulative effect on design performance can be significant. When board parasitics are not modeled during design simulations, their effect on circuit operation is not known until physical prototype testing, where it is expensive to make changes.
Siemens has integrated Xpedition AMS with HyperLynx Advanced 3D Electromagnetic Solvers to provide a unique and powerful solution for calculating layout parasitics and analyzing their effect on a circuit’s function - before committing valuable resources to prototype manufacture and test. The integration also brings analysis of board level parasitics into the circuit design process where it is most efficient to make design changes. Accounting for layout parasitics early in the design process reduces risk of downstream design iterations and is key to keeping a project on time, on budget, and working to specification.