Solido FastSPICE
Accelerated FastSPICE simulation for SoC and memory designs
Modern trends in chip designs, propelled by advancements such as advanced node adoptions and “More than Moore” designs, have significantly increased design complexity. As analog and custom IC designers strive to meet these demands, they encounter formidable obstacles in the form of slow and lengthy simulations that often fail to adequately cover all aspects of verification. The Siemens EDA Solido FastSPICE simulator uniquely delivers.
Solido™ FastSPICE, with multi-resolution technology, is a next-generation fast SPICE simulation tool with scalable accuracy for analog and mixed-signal transistor-level functional verification and memory/analog characterization. It features a unified model for SPICE and Fast SPICE scaling, tunable partitioning, topology/circuit-based detection, multi-rate simulation, table-based device modeling, measurement aware simulation technology, and advanced parasitic reduction modes for the highest performance.
The combined technologies provide circuit designers with a unified simulation interface to achieve simulation results order-of-magnitude faster than traditional SPICE simulation with predictable accuracy. Solido FastSPICE supports industry-standard netlist formats and is integrated into the Symphony™ mixed-signal simulation solution, supporting full-chip SoC verification.