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This workshop delves into the critical process of ensuring compliance for high-speed 112G SerDes interfaces, specifically leveraging AMD Versal devices within the Siemens HyperLynx environment.

Participants will gain hands-on experience in simulating and validating 100's of SerDes channels for both 56G and 112G compliance, with a particular focus on identifying and troubleshooting failures encountered at the challenging 112G data rates. We will explore practical techniques for analyzing simulation results, pinpointing root causes of non-compliance, and implementing effective design modifications to ensure passing results at 112G data rates.

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BONUS! You will also be notified when this additional workshop is available: LPDDR5 Bus Simulation and Verification for AMD Versal Devices with HyperLynx

This workshop provides a comprehensive methodology for simulating and verifying Low Power DDR5 (LPDDR5) memory buses using AMD Versal devices within the Siemens HyperLynx environment. Participants will learn how to set up and simulate an entire LPDDR5 bus, including address/command and data signals. A key highlight of this workshop is the utilization of actual IBIS-AMI models from AMD for both the Versal devices and the DRAM components, ensuring high fidelity and accuracy in simulation results. We will guide attendees through the process of running extensive simulation sweeps to identify optimal drive strengths and On-Die Termination (ODT) settings, crucial for robust LPDDR5 operation. Furthermore, the workshop will cover techniques for verifying complex timing parameters and critical signal integrity metrics, ensuring reliable and compliant LPDDR5 bus performance.