Reset domain crossing design verification closure using advanced data analytics techniques

Complex reset mechanisms are embedded in advanced SoCs to meet low-power and high-performance requirements. Multiple reset domains in a design can cause reset domain crossing (RDC) issues when data from one asynchronous source reset domain propagates to either a different asynchronous, synchronous, or no-reset destination domain. The data generated by the RDC verification tools is very large, consisting of millions of RDC paths. The analysis of this data is a very time consuming and challenging task for design and verification engineers that often involves many iterations. In this paper we will highlight how to automate RDC results analysis using data processing and data analytics techniques to provide faster RDC verification closure.

RDC verification using data mining

In reset domain crossing (RDC) design verification, engineers face a major challenge in fixing the most common RDC problems related to incorrect or missing constraints for reset ordering and reset grouping. Typically, there can be hundreds of RDC paths that may have a common root cause, and if we are able to get some initial information about possible common causes of a number of RDC violations, this data will help users to quickly solve a lot of issues and hence save a lot of time and effort.

The progressive application of supervised data processing and data analytics techniques helps accelerated RDC verification closure by analyzing RDC results to recognize patterns and suggesting set up related constraints.

In a case study we observed that the application of advanced data analytic techniques resulted in a major reduction of unsynchronized RDC crossings detected in a design. RDC verification closure time was reduced from around ten days to less than four, as up to 60% of violations on average were resolved.