Expediting simulation turnaround time with incremental build flows

Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use to constantly validate progress. A big part of enabling that rapid turn-around time is a fast and effective build flow. This paper walks the reader through a few of those options; starting with a simple lump sum build and working through options that enable an optimal SoC build flow.

The Optimal SoC Build Flow

Whether the result is a failed compile, passing simulation, or anything in between, the sooner you get that result, the sooner you get to the next step and closer you get to your ultimate objective: passing silicon. Questa has a few different options for optimizing build flows depending on the application. This paper describes a few of those options, starting with a simple lump sum build and working through simulation options that enable an optimal SoC build flow.

Questa users have a lot of flexibility when it comes to finding the build flow that’s right for them. Whether you’re verifying a small sub-system as a one-person team or an entire SoC with a much larger team, the combination of compiled library partitioning, PDUs, parallelism and elaboration
flow are the tools you need for an optimal build flow and reduced SoC build times.