백서

Catapult for a Power Optimized ESL Hardware Realization Flow

Catapult for a Power Optimized ESL Hardware Realization Flow

This paper describes, in general, the Catapult® flow for exploring low-power architectures, and it discusses in detail the low-power optimization results achieved using the Catapult Low-Power design flow. The case study was conducted using real customer designs. Designs were synthesized using Catapult with and without low-power optimizations turned on. With low-power optimizations on, Catapult uses Siemens EDA's PowerPro® technology under the hood for implementing RTL power optimization techniques and for estimating a design’s power usage.

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관련 자료

Korean Catapult High-Level Synthesis and Verification
Fact Sheet

Korean Catapult High-Level Synthesis and Verification

Korean Verification (HLV) tools and methodologies that enable designers to complete their verification signoff at the C++ level with fast closure for RTL.