AI 가속기 생태계: 개요
상위 수준 합성(High-Level Synthesis)
전 세계 회사들은 Catapult HLS 플랫폼 이용하여 머신러닝 가속기를 설계 및 검증하고 시스템에 연결합니다. 하지만 Siemens Digital Industries Software는 한 단계 더 크게 나아가, 프로젝트를 바로 시작할 수 있는 환경을 AI 설계자들에게 제공하는 AI 가속기 생태계를 제시합니다. 설계자들과 함께 작업한 수년간의 경험을 바탕으로, 이 에코시스템은 IP 라이브러리부터 완전한 툴키트까지의 리소스를 실무 엔지니어에게 제공합니다. 본 백서를 읽고 이 AI 가속기 생태계에 대한 모든 것을 알아보십시오.
관련 자료
CEA: Bridging the Gap Between Neural Network Exploration and Hardware Implementation
CEA presents a methodology that bridges the open-source DL framework N2D2 and Catapult HLS to help reducing the design process of hardware accelerators, making it possible to keep pace with new AI algorithms.
Infineon & Coseda: Facelifting a SystemC System Level Model Towards Physical Prototype – Adoption of High-Level-Synthesis
Infineon & Coseda present on the adoption of High-Level-Synthesis at an existing SystemC system level model.
Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc.
STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP
STMicro presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) and a method to add constraints to the random values generated in UVMF.
Alibaba: Innovating Agile Hardware Development with Catapult HLS
At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.