영상

SPICE Netlist Consolidation

예상 소요 시간: 9분
Terry Meeks, Director of Product Engineering at Siemens EDA, discusses SPICE Netlist consolidation, which streamlines verification while boosting IC design productivity.

In this video, Terry Meeks, Director of Product Engineering at Siemens EDA, delves into the complexities of SPICE netlist consolidation within the circuit verification process. He explains the impact of design size, hierarchy, and network latency on verification efficiency. With Calibre constantly under pressure to improve performance, one critical step in the process involves compiling a logic design into a SPICE netlist format, which can become cumbersome due to design complexity and duplications in hierarchical netlists.

As Terry illustrates, hierarchical designs include multiple levels of blocks and cells, often resulting in duplicate files that need to be accessed repeatedly across a shared network. This duplication, coupled with network traffic fluctuations, causes significant delays and impacts productivity. For instance, a real-world example demonstrated that less than one-third of the total runtime for a Calibre run was actually productive processing time, extending overall runtimes by hours.

To address this issue, Siemens EDA has been exploring automated solutions to streamline SPICE netlist consolidation. Manual approaches, like consolidating files at the command line, pose risks, including file size limitations, naming collisions, and potential errors. Scripted solutions, though feasible, may also introduce processing inefficiencies. Given these challenges, Calibre is developing a more unified approach with the V to LVS utility. This tool is designed to compile netlists in various formats and incorporate SPICE libraries, creating a consolidated, Calibre-ready netlist for downstream use.

By automating the consolidation process, this new feature aims to reduce manual intervention, eliminate duplicate file accesses, and optimize network and processing performance. This innovation will allow design teams to maintain efficient workflows and improve time-to-market by alleviating unnecessary network delays and ensuring consolidated netlists are error-free. Siemens EDA’s SPICE Netlist Consolidation feature, integrated within Calibre's automated flow, represents a valuable advancement in circuit verification, enhancing both speed and reliability for users. Terry emphasizes that, while users may not initially notice these delays, addressing them with an automated consolidation solution will deliver significant productivity gains.

공유

관련 자료