영상
Silicon lifecycle redefines design for test
In this Keynote presentation delivered at ETS 2023, Janusz Rajski, Vice President of Engineering, Tessent, reviews the challenges posed by these issues and examines the feasibility of emerging solutions to address them.
Traditionally, we use deterministic structural tests to achieve high-quality in-chip manufacturing and rely on logic BIST for in-system tests. But the test quality achieved by logic BIST is insufficient. Can a deterministic structural test, periodically applied during in-system, achieve the required high reliability? How can the test quality be improved to reduce test escapes in manufacturing? Can stress tests be refined to reduce early mortality? Can environmental monitoring detect load conditions or aging leading to errors and prevent them from manifesting themselves?