This presentation will show a test methodology for Tessent diagnosis with and without the layout aware feature. The presentation will compare the impact of both flows to final diagnosis outcome. The methodology will describe the flows used, the methodology to validate the flows pre-silicon and finally the outcomes for both methodologies.
The product is using a multi-partition hierarchical design with an SSN bus network. Test patterns are created at a partition level targeting both stuck-at and at-speed fault models. The test patterns are retargeted to full-chip level and a pre-silicon flow was developed to generate dummy failure data from ATE in order to validate the diagnosis flow before silicon arrival.
The post silicon diagnosis flow will be described. This involved porting ATE failure data to required format, mapping to partition level & performing diagnosis, initially without any layout information. The flow is repeated with the layout information included and this process is described.
ATE failure data from silicon is generated to give a dataset to test the flows. A detailed comparison is performed of both flows showing the improvement in the number of failure suspects with the layout aware diagnosis flow. The impact of this layout aware diagnosis flow is demonstrated by the increased ability to isolate strong failure candidates from the data. Recommendations are made for further improvements to the flow based on this conclusion.