The key to success for complex SoCs
The move to AI and ML-type workloads has created an explosion in SoC complexity, as developers try to find a balance between speed, cost, and application flexibility. A functional data-gathering and analytics infrastructure can give both fine-grained information on the chip’s behavior under real operating conditions, and system-level visibility of the functional operation of the entire device. This presentation will demonstrate the use of on-chip functional monitoring to solve some of today's tricky development and validation problems.
AI-driven SoC architectures introduce new levels of complexity in system and software design that strain productivity, delay product launch, and reduce customer adoption.
Design teams need new ways for both chip and software development teams to validate and optimize their designs, applications, drivers, and libraries. A piecemeal solution based on processor-centric debug and software instrumentation make root-cause analysis difficult or impossible. Equally, an insufficiently granular network of interconnect monitors may impact performance. Without visibility on interactions between threads and how they use shared memory, developers can't tune distributed software to take full advantage of the SoC’s parallelism.
By designing in a functional analytics architecture that recognizes those needs early in the project, you can optimize the on-chip analytics infrastructure for data visibility and silicon cost. With the right level of visibility, validation can proceed quickly even in the simulation and emulation environments used for pre-silicon design. That, in turn, helps identify bugs and inefficiencies in the hardware design that would otherwise hinder market adoption. As the embedded system moves into the phase of HW-SW co-optimization, a highly configurable, system-level data platform enables rapid cycles of testing and learning, leading to higher quality, more performant systems.
This presentation demonstrates the use of on-chip functional monitoring to solve some of the thorny development and validation problems. With direct examples drawn from customer experience, we will examine how AI chip designs can be more
quickly and efficiently validated, debugged, deployed and optimized, both before market launch and during the full lifetime of the device.